Field of the Invention
The invention relates to a method for manufacturing a conductor structure for an integrated circuit. The structures of such integrated circuits extend in the submicron range in this context. Integrated circuits have a microelectronic circuit that is applied to a common carrier (substrate) and has a multiplicity of components. The degree of integration, a measure of the number of electronic components on the chip, can be very large scale integration (VLSI), ultra-large scale integration (ULSI) or greater.
Wide-ranging problems occur in particular in the manufacture of the metal layers of an integrated electronic circuit. If the metal layer is implemented with copper, there is the risk of corrosion when structuring the copper. This is due to the fact that, after the etching of the copper, residues of the etching material attack the exposed copper faces. In addition, there is the further disadvantageous factor that during chemical etching copper can only be removed at temperatures at which the photoresist liquefies or even burns. U.S. Pat. No. 4,026,742 discloses a plasma etching method for manufacturing an integrated circuit. Here too there is the problem that, if liquid etching solutions are used, the etching mask, which is manufactured from a photoresistive material, disappears or peels off during the etching, with the result that precise structuring is difficult. In U.S. Pat. No. 4,026,742, it is proposed to overcome this problem by manufacturing the integrated circuit in the reaction chamber with a gas which has a halogen component used in a plasma state with a high-frequency electromagnetic field. The halogenated metal regions are removed by sublimation, vaporization or washing with water or some other suitable solution. In the process, the exposed metal is converted using a reactive halogenated gas in the plasma state into a metal halide and removed in order to structure the electrically conductive metal. The plasma can be produced in the reaction chamber with a high-frequency electromagnetic field. The method is used to produce the desired structure of the metal for electrodes or lines on the semiconductor substrate or other microelectrical carriers. It is used in particular for etching tungsten or molybdenum metal structures. The halogenated gas contains essentially dichloro-difluoromethane. The power source operates with a current of 180 mA at 1200 V and a frequency of 13.56 MHz. Because the plasma is at more than 10,000xc2x0 C., the material of the chamber must be appropriately configured in order to be able to withstand the reactions that take place. It is disadvantageous here that the reaction chamber has to meet particular requirements.
U.S. Pat. No. 5,817,572 discloses a further method for manufacturing connections between connecting channels. In this document, the dual damascene process is described. A dielectric layer is deposited and structured by a two-stage etching process. In the first stage of the etching process, a greater part of the dielectric layer is etched within the contact orifices. In the second step, the connection channels and the rest of the dielectric layer are removed by etching within the contact orifices. The depth of the connection channels is difficult to control owing to the deposition of film and the unequal removal by etching. The depth of the connection channels may be too large in the center of the wafer and too small at the edge of the wafer. This results in large differences in the connection resistances on the same wafer. The deposition of metal is difficult because the contact orifices may have a side ratio (ratio of height to width) of 2:1, 3:1 or more. The large side ratios make sputter deposition virtually impossible. A metal layer can be deposited within the contact orifices and the connection channels by chemical vapor deposition. Nevertheless, connecting materials such as aluminum, copper, gold and silver are not typically deposited using chemical vapor deposition. However, polysilicon and tungsten can be deposited using chemical vapor deposition. The dual damascene process is therefore not very suitable for manufacturing the desired conductor structure or an integrated circuit.
It is accordingly an object of the invention to provide a method for manufacturing a conductor structure for an integrated circuit which overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which the passivation of the metal layer is simple and can be carried out with just a small number of process steps.
With the foregoing and other objects in view there is provide, in accordance with the invention, a method for manufacturing a conductor structure for an integrated circuit. The method includes the steps of providing a structured, insulating layer; applying a first passivation layer to the structured, insulating layer; applying a layer of conductive material to the first passivation layer; applying a second passivation layer to the layer of conductive material; applying a hard mask to the second passivation layer; removing the layer of conductive material in regions defined by the hard mask; and removing the first passivation layer in the regions defined by hard mask by sputtering. Parts of the first passivation layer are at least partially deposited again on a side wall of the layer of conductive material due to the sputtering step.
The layer of conductive material can be removed by reactive ion etching.
The layer of conductive material can also be removed by sputtering.
The layer of conductive material advantageously contains copper. Copper has a relatively low ohmic resistance.
The thickness of the layer of the conductive material is between 300 nm and 500 nm.
The passivation layers can contain tantalum, tantalum nitride or both.
The first insulating layer advantageously contains a silicon oxide or a material with a dielectric constant that is lower than that of silicon oxide.
The hard mask can contain silicon nitride, silicon oxynitride or silicon oxide.
The thickness of the hard mask is advantageously between 100 nm and 300 nm.
The thickness of the first and second passivation layers is advantageously approximately 20 nm in each case.
The surface can be provided with a third passivation layer.
The surface can also be provided with a second insulating layer.
If the surface is provided with a second insulating layer, it has to be subsequently chemical-mechanically polished.
The wafer is advantageously cooled during the sputtering.
It is also advantageous to feed in nitrogen during the sputtering.
The structured, first insulating layer can be produced by reactive ion etching.
The layer of conductive material can be structured by heating the wafer and carrying out subsequent reactive ion etching.
The hard mask can be produced by first depositing the hard mask material by a chemical vapor deposition process. Subsequently, an antireflex layer is applied, over which a photoresist mask is applied. The hard mask material is then removed by etching in the regions provided by the photoresist mask. Finally, the antireflex layer and the photoresist mask are removed.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for manufacturing a conductor structure for an integrated circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.